Invention Grant
- Patent Title: Reception circuit
- Patent Title (中): 接收电路
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Application No.: US13310773Application Date: 2011-12-04
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Publication No.: US08494103B2Publication Date: 2013-07-23
- Inventor: Takayuki Shibasaki
- Applicant: Takayuki Shibasaki
- Applicant Address: JP Kawasaki
- Assignee: Fujitsu Limited
- Current Assignee: Fujitsu Limited
- Current Assignee Address: JP Kawasaki
- Agency: Fujitsu Patent Center
- Priority: JP2010-271775 20101206
- Main IPC: H04L7/00
- IPC: H04L7/00

Abstract:
A reception circuit includes: a sampling circuit to sample an input data signal based on a clock signal and output a sampled signal; a data interpolation circuit to interpolate the sampled signal based on phase information corresponding to the sampled signal and output an interpolated data signal; an interpolation error decision circuit to output an interpolation error based on the sampled signal and the phase information; a decision/equalization circuit to equalize the interpolated data signal using an equalization coefficient set based on the interpolation error, to check an equalized interpolated data signal and to output a checked signal; and a phase detection circuit to generate the phase information based on at least one of the checked signal and the equalized interpolated data signal and output the phase information to the data interpolation circuit and the interpolation error decision circuit.
Public/Granted literature
- US20120140811A1 RECEPTION CIRCUIT Public/Granted day:2012-06-07
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