A circuit for converting Boolean and arithmetic masks includes “m” converting units, wherein m is an integer greater than 1. Each of the m converting unit includes; a first converting unit configured to receive first bits of input data, output one of the first bits as a first output bit, perform an XOR operation with respect to at least part of the first bits, and output an XOR operation result as a first intermediate result bit to a next converting unit in a sequence of converting unit ranging between 2 and n−1th; and an nth converting unit, wherein n is an integer greater than or equal to 2 and less than or equal to m, configured to receive n−1th bits and nth bits of the input data, and at least one of an n−1th intermediate result bit and n−1th output bit from an n−1th converting unit, perform an AND operation and the XOR operation with respect to a first group of the received bits, output an operation result for the first group as an nth output bit, perform the AND operation and the XOR operation with respect to a second group of the received bits, and output an operation result of the second group as an nth intermediate result bit.