Invention Grant
- Patent Title: Efficient check node message transform approximation for LDPC decoder
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Application No.: US12348674Application Date: 2009-01-05
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Publication No.: US08495119B2Publication Date: 2013-07-23
- Inventor: Vladimir Novichkov , Tom Richardson
- Applicant: Vladimir Novichkov , Tom Richardson
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agent Sam Talpalatsky; Nicholas J. Pauley; Joseph Agusta
- Main IPC: G06F7/483
- IPC: G06F7/483

Abstract:
In modern iterative coding systems such as LDPC decoder and turbo-convolutional decoder in which the invention may be used, the core computations can often be reduced to a sequence of additions and subtractions alternating between logarithm and linear domains A computationally efficient and robust approximation method for log and exp functions is described which involves using a simple bit mapping between fixed point fractional data format and floating point format. The method avoids costly lookup tables and complex computations and further reduces the core processing to a sequence of additions and subtractions using alternating fixed point and floating point processing units. The method is well suited for use in highly optimized hardware implementations which can take advantage of modern advances in standard floating point arithmetic circuit design as well as for software implementation on a wide class of processors equipped with FPU where the invention avoids the need for a typical multi-cycle series of log/exp instructions and especially on a SIMD FPU-equipped processors where log/exp functions are typically scalar.
Public/Granted literature
- US20090177869A1 EFFICIENT CHECK NODE MESSAGE TRANSFORM APPROXIMATION FOR LDPC DECODER Public/Granted day:2009-07-09
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