Invention Grant
US08495308B2 Processor, data processing system and method supporting a shared global coherency state 失效
处理器,数据处理系统和支持共享全局一致性状态的方法

Processor, data processing system and method supporting a shared global coherency state
Abstract:
A multiprocessor data processing system includes at least first and second coherency domains, where the first coherency domain includes a system memory and a cache memory. According to a method of data processing, a cache line is buffered in a data array of the cache memory and a state field in a cache directory of the cache memory is set to a coherency state to indicate that the cache line is valid in the data array, that the cache line is held in the cache memory non-exclusively, and that another cache in said second coherency domain may hold a copy of the cache line.
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