Invention Grant
US08495533B2 Synthesizing VHDL multiple wait behavioral FSMs into RT level FSMs by preprocessing
失效
通过预处理将VHDL多等待行为FSM合成到RT级FSM中
- Patent Title: Synthesizing VHDL multiple wait behavioral FSMs into RT level FSMs by preprocessing
- Patent Title (中): 通过预处理将VHDL多等待行为FSM合成到RT级FSM中
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Application No.: US11522036Application Date: 2006-09-16
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Publication No.: US08495533B2Publication Date: 2013-07-23
- Inventor: Gabor Drasny , Gabor Bobok , Ali El-Zein
- Applicant: Gabor Drasny , Gabor Bobok , Ali El-Zein
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent John E. Campbell; Ido Tuchman
- Main IPC: G06F17/50
- IPC: G06F17/50
Abstract:
Preprocessing parallel sequences of “wait” statements and synthesizing these multiple “wait” statements to construct support for RTL tools. This is accomplished by preprocessing a VHDL process with multiple wait statements (referred to as BehFSM) into an equivalent register transfer.
Public/Granted literature
- US20080127126A1 Synthesizing VHDL multiple wait behavioral FSMs into RT level FSMs by preprocessing Public/Granted day:2008-05-29
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