Invention Grant
- Patent Title: Statistical delay and noise calculation considering cell and interconnect variations
- Patent Title (中): 考虑细胞和互连变化的统计延迟和噪声计算
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Application No.: US12928833Application Date: 2010-12-21
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Publication No.: US08495544B2Publication Date: 2013-07-23
- Inventor: Mustafa Celik , Jiayong Le
- Applicant: Mustafa Celik , Jiayong Le
- Applicant Address: US CA Mountain View
- Assignee: Synopsys, Inc.
- Current Assignee: Synopsys, Inc.
- Current Assignee Address: US CA Mountain View
- Agency: Fenwick & West LLP
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
The electrical circuit timing method provides accurate nominal delay together with the delay sensitivities with respect to different circuit elements (e.g., cells, interconnects, etc.) and variational parameters (e.g., process variations; environmental variations). All the sensitivity computations are based on closed-form formulas; as a consequence, the method provides rapidly and at low cost high accuracy and high numerical stability.
Public/Granted literature
- US20110099531A1 Statistical delay and noise calculation considering cell and interconnect variations Public/Granted day:2011-04-28
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