Invention Grant
- Patent Title: Manufacturing method of semiconductor device
- Patent Title (中): 半导体器件的制造方法
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Application No.: US12662910Application Date: 2010-05-11
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Publication No.: US08497060B2Publication Date: 2013-07-30
- Inventor: Koji Hashimoto
- Applicant: Koji Hashimoto
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Finnegan, Henderson, Farabow, Garrett & Dunner, LLP
- Priority: JP2006-108940 20060411
- Main IPC: G03F7/20
- IPC: G03F7/20

Abstract:
A manufacturing method includes forming a stacked film including first/second/third layers on a substrate, forming a first resist pattern on the stacked film, forming a first film pattern by etching the first layer through the first resist pattern, removing the first resist pattern, partially covering the first film pattern with a second resist pattern, slimming the first film pattern exposed from the second resist pattern, forming a second film pattern by etching the second layer exposed from the first layer through the first film pattern, partially covering the second film pattern with a third resist pattern, removing the first film pattern exposed from the third resist pattern, forming sidewall spacers to the second film pattern and remained second layer, removing the remained second layer portion, followed by etching the third layer through the second film pattern and sidewall spacers to form a third film pattern.
Public/Granted literature
- US20100221665A1 Manufacturing method of semiconductor device Public/Granted day:2010-09-02
Information query
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