Invention Grant
- Patent Title: Low triggering voltage DIAC structure
- Patent Title (中): 低触发电压DIAC结构
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Application No.: US12925277Application Date: 2010-10-18
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Publication No.: US08497526B2Publication Date: 2013-07-30
- Inventor: Vladislav Vashchenko , Antonio Gallerano , Peter J. Hopper
- Applicant: Vladislav Vashchenko , Antonio Gallerano , Peter J. Hopper
- Applicant Address: US CA Santa Clara
- Assignee: National Semiconductor Corporation
- Current Assignee: National Semiconductor Corporation
- Current Assignee Address: US CA Santa Clara
- Agent Eugene C. Conser; Wade J. Brady, III; Frederick J. Telecky, Jr.
- Main IPC: H01L29/66
- IPC: H01L29/66
Abstract:
In a DIAC-like device that includes an n+ and a p+ region connected to the high voltage node, and an n+ and a p+ region connected to the low voltage node, at least two MOS devices are formed between the n+ and p+ region connected to the high voltage node, and the n+ and p+ region connected to the low voltage node.
Public/Granted literature
- US20120091501A1 Low triggering voltage DIAC structure Public/Granted day:2012-04-19
Information query
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