Invention Grant
- Patent Title: Chip package
- Patent Title (中): 芯片封装
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Application No.: US13173255Application Date: 2011-06-30
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Publication No.: US08497585B2Publication Date: 2013-07-30
- Inventor: Ming-Chiang Lee
- Applicant: Ming-Chiang Lee
- Applicant Address: TW Kaohsiung
- Assignee: Advanced Semiconductor Engineering, Inc.
- Current Assignee: Advanced Semiconductor Engineering, Inc.
- Current Assignee Address: TW Kaohsiung
- Agency: J.C. Patents
- Priority: TW97147881A 20081209
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/28

Abstract:
A quad flat non-leaded package including a first patterned conductive layer, a second patterned conductive layer, a chip, bonding wires and a molding compound is provided. The first patterned conductive layer defines a first space, and the second patterned conductive layer defines a second space, wherein the first space overlaps the second space and a part of the second patterned conductive layer surrounding the second space. The chip is disposed on the second patterned conductive layer. The bonding wires are connected between the chip and the second patterned conductive layer. The molding compound encapsulates the second patterned conductive layers, the chip and the bonding wires. In addition, a method of manufacturing a quad flat non-leaded package is also provided.
Public/Granted literature
- US20110260327A1 CHIP PACKAGE Public/Granted day:2011-10-27
Information query
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