According to one embodiment, a three-dimensional semiconductor integrated circuit includes first, second and third chips which are stacked, and a common conductor which connects the first, second and third chips from one another. The first chip includes a first multi-leveling circuit, the second chip includes a second multi-leveling circuit, and the third chip includes a decoding circuit. The first multi-leveling circuit includes a first inverter to which binary first data is input and which outputs one of first and second potentials and a first capacitor which is connected between an output terminal of the first inverter and the common conductor. The second multi-leveling circuit includes a second inverter to which binary second data is input and which outputs one of third and fourth potentials and a second capacitor which is connected between an output terminal of the second inverter and the common conductor.