Invention Grant
US08497789B2 Modified dynamic element matching for reduced latency in a pipeline analog to digital converter
有权
改进的动态元素匹配，以减少流水线模数转换器的延迟
- Patent Title: Modified dynamic element matching for reduced latency in a pipeline analog to digital converter
- Patent Title (中): 改进的动态元素匹配，以减少流水线模数转换器的延迟
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Application No.: US13489962Application Date: 2012-06-06
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Publication No.: US08497789B2Publication Date: 2013-07-30
- Inventor: Daniel Meacham , Andrea Panigada , Jorge Grilo
- Applicant: Daniel Meacham , Andrea Panigada , Jorge Grilo
- Applicant Address: US AZ Chandler
- Assignee: Microchip Technology Incorporated
- Current Assignee: Microchip Technology Incorporated
- Current Assignee Address: US AZ Chandler
- Agency: King & Spalding L.L.P.
- Main IPC: H03M1/06
- IPC: H03M1/06
Abstract:
A pipeline ADC is provided in which a DEM function and summation of sequences occur within a flash ADC. According to various aspects of the present disclosure, embedding the processing functions needed for DAC and amplifier error correction with the circuitry of a coarse ADC and rearranging the digital calibration blocks HDC and DNC ensures accurate estimation of the errors.
Public/Granted literature
- US20130002459A1 Modified Dynamic Element Matching For Reduced Latency In A Pipeline Analog To Digital Converter Public/Granted day:2013-01-03
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