Invention Grant
US08498168B2 Test method for screening local bit-line defects in a memory array
有权
用于筛选存储器阵列中局部位线缺陷的测试方法
- Patent Title: Test method for screening local bit-line defects in a memory array
- Patent Title (中): 用于筛选存储器阵列中局部位线缺陷的测试方法
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Application No.: US13085942Application Date: 2011-04-13
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Publication No.: US08498168B2Publication Date: 2013-07-30
- Inventor: Yin Chin Huang , Chu Pang Huang , Yi Fang Chang , Cheng Chi Liu , Chang Chan Yang , Min Kuang Lee
- Applicant: Yin Chin Huang , Chu Pang Huang , Yi Fang Chang , Cheng Chi Liu , Chang Chan Yang , Min Kuang Lee
- Applicant Address: TW Hsin-Chu
- Assignee: Macronix International Co., Ltd.
- Current Assignee: Macronix International Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Alston & Bird LLP
- Main IPC: G11C7/00
- IPC: G11C7/00

Abstract:
A method of detecting manufacturing defects at a memory array may include utilizing test circuitry to provide a selected voltage as drain bias on a bit-line of the memory array where the memory array is configured to employ a first voltage as the drain bias for a read operation and the selected voltage is higher than the first voltage, and determining whether a leakage current indicative of a manufacturing defect between the bit-line and another component of the memory array is present responsive to providing the selected voltage as the drain bias. A corresponding test device is also provided.
Public/Granted literature
- US20120263002A1 TEST METHOD FOR SCREENING LOCAL BIT-LINE DEFECTS IN A MEMORY ARRAY Public/Granted day:2012-10-18
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