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US08498168B2 Test method for screening local bit-line defects in a memory array 有权
用于筛选存储器阵列中局部位线缺陷的测试方法

Test method for screening local bit-line defects in a memory array
Abstract:
A method of detecting manufacturing defects at a memory array may include utilizing test circuitry to provide a selected voltage as drain bias on a bit-line of the memory array where the memory array is configured to employ a first voltage as the drain bias for a read operation and the selected voltage is higher than the first voltage, and determining whether a leakage current indicative of a manufacturing defect between the bit-line and another component of the memory array is present responsive to providing the selected voltage as the drain bias. A corresponding test device is also provided.
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