An apparatus including an input circuit, a control circuit, a queue, an aggregation circuit, and an output circuit. The input circuit is configured to receive packets. The control circuit is configured to enable aggregation when a rate at which the input circuit receives the packets is greater than a predetermined rate. The queue is configured to store the packets from the input circuit when aggregation is enabled. The aggregation circuit is configured to generate aggregate packets when aggregation is enabled. The aggregation circuit is configured to generate each of the aggregate packets by aggregating at least one of the packets stored in the queue. The output circuit is configured to receive (i) the aggregate packets when aggregation is enabled and (ii) the packets from the input circuit when aggregation is disabled.