Invention Grant
US08498831B2 Semiconductor device, semiconductor device testing method, and data processing system
失效
半导体器件,半导体器件测试方法和数据处理系统
- Patent Title: Semiconductor device, semiconductor device testing method, and data processing system
- Patent Title (中): 半导体器件,半导体器件测试方法和数据处理系统
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Application No.: US12923831Application Date: 2010-10-08
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Publication No.: US08498831B2Publication Date: 2013-07-30
- Inventor: Akira Ide , Hideyuki Yoko , Kayoko Shibata , Kenichi Tanamachi , Takanori Eguchi , Yasuyuki Shigezane , Naoki Ogawa , Kazuo Hidaka
- Applicant: Akira Ide , Hideyuki Yoko , Kayoko Shibata , Kenichi Tanamachi , Takanori Eguchi , Yasuyuki Shigezane , Naoki Ogawa , Kazuo Hidaka
- Applicant Address: JP Tokyo
- Assignee: Elpida Memory, Inc.
- Current Assignee: Elpida Memory, Inc.
- Current Assignee Address: JP Tokyo
- Agency: McGinn IP Law Group, PLLC
- Priority: JP2009-235481 20091009; JP2010-198492 20100906; JP2010-227865 20101007
- Main IPC: G06F19/00
- IPC: G06F19/00

Abstract:
To include one or a plurality of internal signal lines that electrically connects an interface chip to a core chip. The interface chip includes a first circuit that outputs a current to an internal wiring and the core chip includes a second circuit that outputs a current to the first internal signal line. The interface chip includes a determination circuit that has a first input terminal connected to the internal wiring through which the current outputted by the first circuit flows and a second input terminal connected to an end of the first internal signal line in the interface chip, and outputs a voltage according to a potential difference between a voltage of the first input terminal and a voltage of the second input terminal.
Public/Granted literature
- US20110093224A1 Semiconductor device, semiconductor device testing method, and data processing system Public/Granted day:2011-04-21
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