Invention Grant
US08498855B2 Circuit simulation based on gate spacing from adjacent MOS transistors
有权
基于相邻MOS晶体管栅极间距的电路仿真
- Patent Title: Circuit simulation based on gate spacing from adjacent MOS transistors
- Patent Title (中): 基于相邻MOS晶体管栅极间距的电路仿真
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Application No.: US12585850Application Date: 2009-09-25
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Publication No.: US08498855B2Publication Date: 2013-07-30
- Inventor: Hideo Sakamoto
- Applicant: Hideo Sakamoto
- Applicant Address: JP Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kanagawa
- Agency: Foley & Lardner LLP
- Priority: JP2008-247920 20080926
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G06F9/455

Abstract:
A circuit simulation apparatus is provided with a parameter calculating tool and a circuit simulator. The parameter calculating tool is configured to extract gate spacings between gates of a target MOS transistor and adjacent MOS transistors integrated in an integrated circuit from layout data of the integrated circuit, and to calculate a transistor model parameter corresponding to a threshold voltage of the target MOS transistor based on the extracted gate spacings. The circuit simulator is configured to perform circuit simulation of the integrated circuit by using the calculated transistor model parameter.
Public/Granted literature
- US20100082308A1 Circuit simulation based on gate spacing from adjacent MOS transistors Public/Granted day:2010-04-01
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