Invention Grant
US08499207B2 Memory devices and method for error test, recordation and repair
有权
内存设备和方法进行错误测试,记录和修复
- Patent Title: Memory devices and method for error test, recordation and repair
- Patent Title (中): 内存设备和方法进行错误测试,记录和修复
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Application No.: US13559942Application Date: 2012-07-27
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Publication No.: US08499207B2Publication Date: 2013-07-30
- Inventor: Christian N. Mohr , Timothy B. Cowles
- Applicant: Christian N. Mohr , Timothy B. Cowles
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: TraskBritt
- Main IPC: G11C29/00
- IPC: G11C29/00 ; G06F11/00

Abstract:
In a memory device, an on-die register is provided that is configured to store a row address as well as a column address of a memory cell that fails a test. Storing the row address frees testing from being limited to activating at one time only rows related to a common redundant segment. Storing the row address also guides repair using segmented redundancy. As an addition or alternative, information may be stored in an anti-fuse bank that is designed to provide access to a redundant cell but has not yet enabled access to that cell. If the information stored in the anti-fuse bank relates to the failure of the redundant cell, such information may be used to avoid repairing with that redundant cell.
Public/Granted literature
- US20120297257A1 MEMORY DEVICES AND METHOD FOR ERROR TEST, RECORDATION AND REPAIR Public/Granted day:2012-11-22
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