Invention Grant
- Patent Title: Method and apparatus for scheduling BIST routines
- Patent Title (中): 调度BIST例程的方法和装置
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Application No.: US11553609Application Date: 2006-10-27
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Publication No.: US08499208B2Publication Date: 2013-07-30
- Inventor: James Norris Dieffenderfer , Anand Krishnamurthy , Clint Wayne Mumford , Jason Lawrence Panavich , Ketan Vitthal Patel , Ravi Rajagopalan , Thomas Philip Speier
- Applicant: James Norris Dieffenderfer , Anand Krishnamurthy , Clint Wayne Mumford , Jason Lawrence Panavich , Ketan Vitthal Patel , Ravi Rajagopalan , Thomas Philip Speier
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agent Nicholas J. Pauley; Sam Talpalatsky; Joseph Agusta
- Main IPC: G01R31/28
- IPC: G01R31/28

Abstract:
The content and order of a predetermined sequence of hard-coded and/or quasi-programmable test patterns may be altered during a Built-In Self-Test (BIST) routine. As such, knowledge gained post design completion may be reflected in the selection and arrangement of available tests to be executed during a BIST routine. In one embodiment, a sequence of hard-coded and/or quasi-programmable tests is executed during a BIST routine by receiving test ordering information for the sequence of tests and executing the sequence of tests in an order indicated by the test ordering information. A corresponding BIST circuit comprises a storage element and a state machine. The storage element is configured to store test ordering information for the sequence of tests. The state machine is configured to execute the sequence of tests in an order indicated by the test ordering information.
Public/Granted literature
- US20080115026A1 Method and Apparatus for Scheduling BIST Routines Public/Granted day:2008-05-15
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