A circuit for preventing a setup fail between a first latch and a second latch according to one embodiment of the present invention comprises a mimic combinational logic module and a clock compare module. The mimic combinational logic module is configured to receive a first clock signal for the first latch and to generate a delayed first clock signal, which is a delayed version of the first clock signal. The clock compare module is configured to provide a delayed second clock signal, which is a delayed version of a second clock signal for the second latch, to the second latch after receiving the delayed first clock signal and the second clock signal.