Invention Grant
US08499272B2 Semiconductor device based on power gating in multilevel wiring structure
有权
基于多层布线结构中功率门控的半导体器件
- Patent Title: Semiconductor device based on power gating in multilevel wiring structure
- Patent Title (中): 基于多层布线结构中功率门控的半导体器件
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Application No.: US13434654Application Date: 2012-03-29
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Publication No.: US08499272B2Publication Date: 2013-07-30
- Inventor: Toshinao Ishii
- Applicant: Toshinao Ishii
- Applicant Address: JP Tokyo
- Assignee: Elpida Memory, Inc.
- Current Assignee: Elpida Memory, Inc.
- Current Assignee Address: JP Tokyo
- Agency: McGinn IP Law Group, PLLC
- Priority: JP2011-079399 20110331
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A semiconductor device includes: first and second circuit cell arrays extending in first direction; first and second power supply lines each extending in first direction and arranged over first circuit cell array, first power supply line being supplied with first power source voltage; third power supply line extending in first direction separately from second power supply line, arranged over second circuit cell array, and supplied with second power source voltage; first transistor coupled between second and third power supply lines; and first circuit arranged on first circuit cell array and operating on first and second power source voltages supplied from first and second power supply lines, respectively.
Public/Granted literature
- US20120249226A1 SEMICONDUCTOR DEVICE Public/Granted day:2012-10-04
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