The electronic circuit is intended to form with an antenna a responder that operates without resetting to zero when the power supply of the electronic circuit is switched on (without POR). To increase efficiency and reduce the costs of testing a plurality of such integrated circuits in a wafer, means are provided that allow the logic circuit (8) to be reset to zero during such a test by electrical contact with the pads (P1, P2) of each circuit by using two extractors (12 and 14) of clock signals (CL1 and CL2) connected to the inputs of a generator (20) of a zero reset signal (SR). The state of the generator is essentially given by the difference in pulses received from the two clock signal extractors. As soon as the state of the generator corresponds to a value equal to or greater than a predefined integer, the logic circuit is reset to zero, which never occurs with the responder receiving an interrogation signal of a reader.