Invention Grant
- Patent Title: Method of manufacturing devices having vertical junction edge
- Patent Title (中): 制造具有垂直接合边缘的器件的方法
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Application No.: US13336516Application Date: 2011-12-23
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Publication No.: US08501602B2Publication Date: 2013-08-06
- Inventor: Fernando Gonzalez , Chandra Mouli
- Applicant: Fernando Gonzalez , Chandra Mouli
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Fletcher Yoder
- Main IPC: H01L21/425
- IPC: H01L21/425

Abstract:
Techniques for forming devices, such as transistors, having vertical junction edges. More specifically, shallow trenches are formed in a substrate and filled with an oxide. Cavities may be formed in the oxide and filled with a conductive material, such a doped polysilicon. Vertical junctions are formed between the polysilicon and the exposed substrate at the trench edges such that during a thermal cycle, the doped polysilicon will out-diffuse doping elements into the adjacent single crystal silicon advantageously forming a diode extension having desirable properties.
Public/Granted literature
- US20120108033A1 METHOD OF MANUFACTURING DEVICES HAVING VERTICAL JUNCTION EDGE Public/Granted day:2012-05-03
Information query
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