Semiconductor devices including a topmost metal layer with at least one opening and their methods of fabrication

Invention Grant

US08501617B2 Semiconductor devices including a topmost metal layer with at least one opening and their methods of fabrication 有权

Title translation: 包括具有至少一个开口的最顶层金属层及其制造方法的半导体器件

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Patent Title: Semiconductor devices including a topmost metal layer with at least one opening and their methods of fabrication
Patent Title (中): 包括具有至少一个开口的最顶层金属层及其制造方法的半导体器件
Application No.: US12855870

Application Date: 2010-08-13
Publication No.: US08501617B2

Publication Date: 2013-08-06
Inventor: Joo-Sung Park , Ae-Ran Hong
Applicant: Joo-Sung Park , Ae-Ran Hong
Applicant Address: KR Suwon-Si, Gyeonggi-Do
Assignee: Samsung Electronics Co., Ltd.
Current Assignee: Samsung Electronics Co., Ltd.
Current Assignee Address: KR Suwon-Si, Gyeonggi-Do
Agency: F. Chau & Associates, LLC
Priority: KR2005-52654 20050617
Main IPC: H01L21/4763
IPC: H01L21/4763

Semiconductor devices including a topmost metal layer with at least one opening and their methods of fabrication

Abstract:

In one embodiment, a semiconductor device has a topmost or highest conductive layer with at least one opening. The semiconductor device includes a semiconductor substrate having a cell array region and an interlayer insulating layer covering the substrate having the cell array region. The topmost conductive layer is disposed on the interlayer insulating layer in the cell array region. The topmost conductive layer has at least one opening. A method of fabricating the semiconductor device is also provided. The openings penetrating the topmost metal layer help hydrogen atoms reach the interfaces of gate insulating layers of cell MOS transistors and/or peripheral MOS transistors during a metal alloy process, thereby improve a performance (production yield and/or refresh characteristics) of a memory device.

Abstract(Chinese):

在一个实施例中，半导体器件具有至少一个开口的最顶层或最高导电层。半导体器件包括具有单元阵列区域的半导体衬底和覆盖具有单元阵列区域的衬底的层间绝缘层。最上面的导电层设置在电池阵列区域中的层间绝缘层上。最上面的导电层具有至少一个开口。还提供了制造半导体器件的方法。穿过最顶层金属层的开口在金属合金工艺期间帮助氢原子到达单元MOS晶体管和/或外围MOS晶体管的栅极绝缘层的界面，从而提高存储器件的性能（生产产量和/或刷新特性）。

Public/Granted literature

US20100304537A1 Semiconductor Devices Including a Topmost Metal Layer with at Least one Opening and Their Methods of Fabrication Public/Granted day:2010-12-02

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IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/02	.半导体器件或其部件的制造或处理
H01L21/04	..至少具有一个跃变势垒或表面势垒的器件，例如PN结、耗尽层、载体集结层
H01L21/34	...具有H01L21/06，H01L21/16及H01L21/18各组不包含的或有或无杂质，例如掺杂材料的半导体的器件
H01L21/46	....用H01L21/36至H01L21/428各组不包含的方法或设备处理半导体材料的（在半导体材料上制作电极的入H01L21/44）
H01L21/461	.....改变半导体材料的表面物理特性或形状的，例如腐蚀、抛光、切割
H01L21/4763	......非绝缘层的沉积，例如绝缘层上的导电层、电阻层；这些层的后处理（电极的制造入H01L21/28）