Invention Grant
- Patent Title: Silicon wafer having testing pad(s) and method for testing the same
- Patent Title (中): 具有测试垫的硅晶片及其测试方法
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Application No.: US12726812Application Date: 2010-03-18
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Publication No.: US08502223B2Publication Date: 2013-08-06
- Inventor: Chi-Han Chen
- Applicant: Chi-Han Chen
- Applicant Address: TW Kaohsiung
- Assignee: Advanced Semiconductor Engineering, Inc.
- Current Assignee: Advanced Semiconductor Engineering, Inc.
- Current Assignee Address: TW Kaohsiung
- Agency: McCracken & Frank LLC
- Priority: TW98114521A 20090430
- Main IPC: H01L23/58
- IPC: H01L23/58 ; H01L23/48

Abstract:
The present invention relates to a silicon wafer having testing pad(s) and a method for testing the same. The silicon wafer includes a silicon substrate, an insulation layer, at least one testing pad and a dielectric layer. The testing pad includes a first metal layer, a second metal layer and at least one first interconnection metal. The first metal layer is disposed on the insulation layer, and has a first area and a second area. The first area and the second area are electrically insulated with each other. The second metal layer is disposed above the first metal layer. The first interconnection metal connects the second area of the first metal layer and the second metal layer. Therefore, when a through hole and a seed layer are formed in the following processes, the through hole is estimated whether it is qualified by probing the testing pad to know whether the seed layer connects the second area of the first metal layer of the testing pad, thus the yield rate of the following processes is increased.
Public/Granted literature
- US20100276690A1 Silicon Wafer Having Testing Pad(s) and Method for Testing The Same Public/Granted day:2010-11-04
Information query
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