Invention Grant
- Patent Title: Multi-level options for power MOSFETS
- Patent Title (中): 功率MOSFET的多级选项
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Application No.: US13091681Application Date: 2011-04-21
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Publication No.: US08502314B2Publication Date: 2013-08-06
- Inventor: Thomas E. Grebs , Jayson S. Preece
- Applicant: Thomas E. Grebs , Jayson S. Preece
- Applicant Address: US CA San Jose
- Assignee: Fairchild Semiconductor Corporation
- Current Assignee: Fairchild Semiconductor Corporation
- Current Assignee Address: US CA San Jose
- Agency: Schwegman Lundberg & Woessner P.A.
- Main IPC: H01L29/76
- IPC: H01L29/76

Abstract:
This document discusses, among other things, a semiconductor device including first and second conductive layers, the first conductive layer including a gate runner and a drain contact and the second conductive layer including a drain conductor, at least a portion of the drain conductor overlying at least a portion of the gate runner. A first surface of the semiconductor device can include a gate pad coupled to the gate runner and a drain pad coupled to the drain contact and the drain conductor.
Public/Granted literature
- US20120267711A1 MULTI-LEVEL OPTIONS FOR POWER MOSFETS Public/Granted day:2012-10-25
Information query
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