Invention Grant
- Patent Title: Break pattern of silicon wafer, silicon wafer, and silicon substrate
- Patent Title (中): 硅晶片,硅晶片和硅基板的断裂图案
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Application No.: US13570753Application Date: 2012-08-09
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Publication No.: US08502354B2Publication Date: 2013-08-06
- Inventor: Isamu Togashi
- Applicant: Isamu Togashi
- Applicant Address: JP Tokyo
- Assignee: Seiko Epson Corporation
- Current Assignee: Seiko Epson Corporation
- Current Assignee Address: JP Tokyo
- Agency: Workman Nydegger
- Priority: JP2011-176522 20110812
- Main IPC: H01L23/544
- IPC: H01L23/544

Abstract:
A break pattern of a silicon wafer includes a line to be cut which is set in the silicon wafer assuming a surface as a (110) face in a surface direction of a first (111) face perpendicular to the (110) face; and through holes which are provided in a plurality of rows on the line to be cut, wherein each of the through holes has a first (111) face, a second (111) face which intersects the first (111) face, and a third (111) face which intersects the second (111) face and the first (111) face, an intersecting point with end edges of the second (111) face and the third (111) face is assumed as a point closest to the adjacent through holes.
Public/Granted literature
- US20130037916A1 BREAK PATTERN OF SILICON WAFER, SILICON WAFER, AND SILICON SUBSTRATE Public/Granted day:2013-02-14
Information query
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