Invention Grant
US08502376B2 Wirebondless wafer level package with plated bumps and interconnects
有权
无铅晶圆级封装,带有电镀凸块和互连
- Patent Title: Wirebondless wafer level package with plated bumps and interconnects
- Patent Title (中): 无铅晶圆级封装,带有电镀凸块和互连
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Application No.: US13101657Application Date: 2011-05-05
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Publication No.: US08502376B2Publication Date: 2013-08-06
- Inventor: Zigmund R. Camacho , Dioscoro A. Merilo , Lionel Chien Hui Tay , Jose A. Caparas
- Applicant: Zigmund R. Camacho , Dioscoro A. Merilo , Lionel Chien Hui Tay , Jose A. Caparas
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC, Ltd.
- Current Assignee: STATS ChipPAC, Ltd.
- Current Assignee Address: SG Singapore
- Agency: Patent Law Group: Atkins & Associates, P.C.
- Agent Robert D. Atkins
- Main IPC: H01L23/498
- IPC: H01L23/498

Abstract:
A semiconductor package includes a carrier strip having a die cavity and bump cavities. A semiconductor die is mounted in the die cavity of the carrier strip. In one embodiment, the semiconductor die is mounted using a die attach adhesive. In one embodiment, a top surface of the first semiconductor die is approximately coplanar with a top surface of the carrier strip proximate to the die cavity. A metal layer is disposed over the carrier strip to form a package bump and a plated interconnect between the package bump and a contact pad of the first semiconductor die. An underfill material is disposed in the die cavity between the first semiconductor die and a surface of the die cavity. A passivation layer is disposed over the first semiconductor die and exposes a contact pad of the first semiconductor die. An encapsulant is disposed over the carrier strip.
Public/Granted literature
- US20110204512A1 Wirebondless Wafer Level Package with Plated Bumps and Interconnects Public/Granted day:2011-08-25
Information query
IPC分类: