Invention Grant
US08502377B2 Package substrate for bump on trace interconnection 有权
封装衬底,用于跟踪互连上的凹凸

Package substrate for bump on trace interconnection
Abstract:
A package substrate including a conductive pattern disposed on a die attach surface of the package substrate; at least one bumping trace inlaid into the conductive pattern; and at least one gap disposed along with the bumping trace in the conductive pattern to separate the bumping trace from a bulk portion of the conductive pattern. The bumping trace may have a lathy shape from a plan view and a width substantially between 10 μm and 40 μm and a length substantially between 70 μm and 130 μm, for example.
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