Invention Grant
- Patent Title: Adaptive digital phase locked loop
- Patent Title (中): 自适应数字锁相环
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Application No.: US13543529Application Date: 2012-07-06
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Publication No.: US08502582B2Publication Date: 2013-08-06
- Inventor: Nathaniel J. August , Hyung-Jin Lee
- Applicant: Nathaniel J. August , Hyung-Jin Lee
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: H03L7/06
- IPC: H03L7/06
Abstract:
In some embodiments, a digital PLL (DPLL) is disclosed with a dynamically controllable filter for changing the effective DPLL bandwidth in response to one or more real-time performance parameters such as phase error.
Public/Granted literature
- US20120280729A1 ADAPTIVE DIGITAL PHASE LOCKED LOOP Public/Granted day:2012-11-08
Information query
