Invention Grant
- Patent Title: Power down enabled analog switch
- Patent Title (中): 断电启用模拟开关
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Application No.: US13428218Application Date: 2012-03-23
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Publication No.: US08502595B2Publication Date: 2013-08-06
- Inventor: Julie Lynn Stultz , James Joseph Morra , Steven Macaluso
- Applicant: Julie Lynn Stultz , James Joseph Morra , Steven Macaluso
- Applicant Address: US CA San Jose
- Assignee: Fairchild Semiconductor Corporation
- Current Assignee: Fairchild Semiconductor Corporation
- Current Assignee Address: US CA San Jose
- Agency: Schwegman Lundberg & Woessner P.A.
- Main IPC: H03K17/56
- IPC: H03K17/56

Abstract:
This document discusses, among other things, apparatus and methods for passing a signal in a power down state. An example switch device can include a first depletion-mode transistor configured to pass an analog signal between a first node and a second node in a first state and to isolate the first node from the second node in a second state, a control circuit coupled to a control node of the first depletion-mode transistor and configured to isolate the control node from a first supply input in the first state and to couple the control node to the first supply input in the second state, and a tracking circuit configured to couple the control node of the first depletion-mode transistor to the first node during the first state and to isolate the control node of the first depletion-mode transistor from the first node in the second state.
Public/Granted literature
- US20120242397A1 POWER DOWN ENABLED ANALOG SWITCH Public/Granted day:2012-09-27
Information query
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