This invention relates to a coding circuit for generating a swap tolerant code. The coding circuit comprises a first and second input (540, 541), an odd parity pair detector (535), a memory (533), and an output circuit (536, 537, 551; 736, 737, 751). Each of the first and second inputs (540, 541) receive a stream of serial data. The odd parity pair detector (535) outputs an odd parity pair signal if the bits received at said first and second inputs (540, 541) have different logical values and therefore constitute an odd parity pair. The memory (533) stores information on a previous odd parity pair. The output circuit outputs the previous odd parity pair, if said first input (540) provides a logical 1 and said second input (541) provides a logical 0. The output circuit outputs the inverted previous odd parity pair, if said first input (540) provides a logical 0 and said second input (541) provides a logical 1. The invention further provides a corresponding decoding circuit, and coding and decoding methods. Further the invention relates to a coding circuit for inversion tolerant coding, a corresponding decoding circuit and coding and decoding methods.