Invention Grant
US08503244B2 Fabricating and operating a memory array having a multi-level cell region and a single-level cell region 有权
制造和操作具有多级单元区域和单级单元区域的存储器阵列

Fabricating and operating a memory array having a multi-level cell region and a single-level cell region
Abstract:
Techniques are disclosed herein for applying different process steps to single-level cell (SLC) blocks in a memory array than to multi-level cell (MLC) blocks such that the SLC blocks will have high endurance and the MLC blocks will have high reliability. In some aspects, different doping is used in the MLC blocks than the SLC blocks. In some aspects, different isolation is used in the MLC blocks than the SLC blocks. Techniques are disclosed that apply different read parameters depending on how many times a block has been programmed/erased. Therefore, blocks that have been cycled many times are read using different parameters than blocks that have been cycled fewer times.
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