According to one embodiment, a semiconductor storage device includes a memory cell array and a control circuit. The memory cell array has memory cells arranged therein at respective intersections between a plurality of first wirings and a plurality of second wirings. Each of the memory cells has a variable resistance element. The control circuit is configured to apply a voltage to a selected one of the first wirings and to a selected one of the second wirings. The control circuit includes a plurality of charge pump circuits and a plurality of clock oscillator circuits. The charge pump circuits generate a voltage applied to the first and second wirings. Each of the clock oscillator circuits is configured to supply a clock signal to a certain number of the charge pump circuits to control the timing of operation thereof. The clock oscillator circuits are configured to output clock signals at different frequencies.