Invention Grant
US08503259B2 Memory test method and memory test device 有权
内存测试方法和内存测试设备

Memory test method and memory test device
Abstract:
A memory test is performed by sequentially generating a number of n-bit addresses, whose first to k-th bits (1≦k≦n) are all set to one of two values, 0 or 1, and whose (k+1)th to n-th bits are all set to the other one of the two values, for all k's which range from 1 to n; writing first test data to each of the generated addresses in the memory; reading second test data from each of the addresses in the memory; and comparing the first test data with the second test data.
Public/Granted literature
Information query
Patent Agency Ranking
0/0