Invention Grant
- Patent Title: Memory test method and memory test device
- Patent Title (中): 内存测试方法和内存测试设备
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Application No.: US12382485Application Date: 2009-03-17
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Publication No.: US08503259B2Publication Date: 2013-08-06
- Inventor: Shogo Shibazaki , Shinkichi Gama , Hideyuki Negi , Takeshi Nagase , Chikahiro Deguchi , Yutaka Sekino
- Applicant: Shogo Shibazaki , Shinkichi Gama , Hideyuki Negi , Takeshi Nagase , Chikahiro Deguchi , Yutaka Sekino
- Applicant Address: JP Kawasaki
- Assignee: Fujitsu Limited
- Current Assignee: Fujitsu Limited
- Current Assignee Address: JP Kawasaki
- Agency: Staas & Halsey LLP
- Priority: JP2008-143893 20080530
- Main IPC: G11C29/00
- IPC: G11C29/00

Abstract:
A memory test is performed by sequentially generating a number of n-bit addresses, whose first to k-th bits (1≦k≦n) are all set to one of two values, 0 or 1, and whose (k+1)th to n-th bits are all set to the other one of the two values, for all k's which range from 1 to n; writing first test data to each of the generated addresses in the memory; reading second test data from each of the addresses in the memory; and comparing the first test data with the second test data.
Public/Granted literature
- US20090296505A1 Memory test method and memory test device Public/Granted day:2009-12-03
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