A video system includes a central processing unit (CPU) and a graphic processing unit (GPU) including a plurality of processors therein. The system also includes a high definition (HD) imager; a serial bus controller coupled to the imager, the CPU and the GPU to communicate data between the HD imager and the CPU or the GPU over a serial bus having a transmit differential signal pair, a receive differential pair and a compatibility differential signal pair for interoperability with another serial bus version; and computer code executable by the processors in the GPU to encode in parallel the video transmitted over the serial bus controller and to minimize high definition encoding workload on the CPU.