Invention Grant
US08503678B2 Suppressing power supply noise using data scrambling in double data rate memory systems
有权
使用双数据速率存储器系统中的数据扰频抑制电源噪声
- Patent Title: Suppressing power supply noise using data scrambling in double data rate memory systems
- Patent Title (中): 使用双数据速率存储器系统中的数据扰频抑制电源噪声
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Application No.: US12646823Application Date: 2009-12-23
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Publication No.: US08503678B2Publication Date: 2013-08-06
- Inventor: Maynard C. Falconer , Christopher P. Mozak , Adam J. Norman
- Applicant: Maynard C. Falconer , Christopher P. Mozak , Adam J. Norman
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: G06F21/00
- IPC: G06F21/00

Abstract:
Embodiments are generally directed to systems, methods, and apparatuses for suppressing power supply noise using data scrambling in double data rate memory systems. In some embodiments, an integrated circuit includes a transmit data path to transmit data to one or more memory devices. The transmit data path may include scrambling logic to generate, in parallel, N pseudo random outputs that are uncorrelated with each other. The output data and the pseudo random outputs are input to XOR logic. The transmit data path transmits the output the of XOR logic which has a substantially white frequency spectrum. Other embodiments are described and claimed.
Public/Granted literature
- US20100153699A1 SUPPRESSING POWER SUPPLY NOISE USING DATA SCRAMBLING IN DOUBLE DATA RATE MEMORY SYSTEMS Public/Granted day:2010-06-17
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