A simulation apparatus that performs simulation of design data of a verification target circuit including a logic circuit that operates as a multi-cycle path of N cycles in synchronization with a clock signal, the simulation apparatus includes a design data generation section that generates design data of a multi-cycle verification circuit for selectively providing an undefined value signal in place of a signal in a multi-cycle part in the verification target circuit; a logical simulation section that performs logical simulation, without delay, on the basis of design data of the verification target circuit and the design data of the multi-cycle verification circuit; and a comparison section that compares the signal of the verification target circuit with a signal of an expected value in the verification target circuit in the logical simulation.