Invention Grant
US08504777B2 Data processor for processing decorated instructions with cache bypass
有权
用于处理具有缓存旁路的装饰指令的数据处理器
- Patent Title: Data processor for processing decorated instructions with cache bypass
- Patent Title (中): 用于处理具有缓存旁路的装饰指令的数据处理器
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Application No.: US12886641Application Date: 2010-09-21
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Publication No.: US08504777B2Publication Date: 2013-08-06
- Inventor: William C. Moyer
- Applicant: William C. Moyer
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Agent Joanna G. Chiu; David G. Dolezal
- Main IPC: G06F13/20
- IPC: G06F13/20

Abstract:
A method includes determining if a data processing instruction is a decorated access instruction with cache bypass, and determining if the data processing instruction generates a cache hit to a cache. When the data processing instruction is determined to be a decorated access instruction with cache bypass and the data processing instruction is determined to generate a cache hit, the method further includes invalidating a cache entry of the cache associated with the cache hit; and performing by a memory controller of the memory, a decoration operation specified by the data processor instruction on a location in the memory designated by a target address of the data processor instruction, wherein the performing the decorated access includes the memory controller performing a read of a value of the location in memory, modifying the value to generate a modified value, and writing the modified value to the location.
Public/Granted literature
- US20120072675A1 DATA PROCESSOR FOR PROCESSING DECORATED INSTRUCTIONS WITH CACHE BYPASS Public/Granted day:2012-03-22
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