Invention Grant
US08504884B2 Threshold voltage techniques for detecting an imminent read failure in a memory array
有权
用于检测存储器阵列中即将发生的读取故障的阈值电压技术
- Patent Title: Threshold voltage techniques for detecting an imminent read failure in a memory array
- Patent Title (中): 用于检测存储器阵列中即将发生的读取故障的阈值电压技术
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Application No.: US12608405Application Date: 2009-10-29
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Publication No.: US08504884B2Publication Date: 2013-08-06
- Inventor: Richard K. Eguchi , Thomas S. Harp , Thomas Jew , Peter J. Kuhn , Timothy J. Strauss
- Applicant: Richard K. Eguchi , Thomas S. Harp , Thomas Jew , Peter J. Kuhn , Timothy J. Strauss
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Agency: Yudell Isidore Ng Russell PLLC
- Main IPC: G11C29/00
- IPC: G11C29/00

Abstract:
A technique for detecting an imminent read failure in a memory array includes determining whether a memory array, which does not exhibit an uncorrectable error correcting code (ECC) read during an initial array integrity check at a normal read verify voltage level, exhibits an uncorrectable ECC read during a subsequent array integrity check at a margin read verify voltage level. The technique also includes providing an indication of an imminent read failure for the memory array when the memory array exhibits an uncorrectable ECC read during the subsequent array integrity check. In this case, the margin read verify voltage level is different from the normal read verify voltage level.
Public/Granted literature
- US20110107161A1 THRESHOLD VOLTAGE TECHNIQUES FOR DETECTING AN IMMINENT READ FAILURE IN A MEMORY ARRAY Public/Granted day:2011-05-05
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