Invention Grant
US08507957B2 Integrated circuit layouts with power rails under bottom metal layer
有权
集成电路布局与底部金属层下的电源轨
- Patent Title: Integrated circuit layouts with power rails under bottom metal layer
- Patent Title (中): 集成电路布局与底部金属层下的电源轨
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Application No.: US13098925Application Date: 2011-05-02
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Publication No.: US08507957B2Publication Date: 2013-08-13
- Inventor: Yung-Chin Hou , Shyue-Shyh Lin , Li-Chun Tien , Shu-Min Chen , Pin-Dai Sue
- Applicant: Yung-Chin Hou , Shyue-Shyh Lin , Li-Chun Tien , Shu-Min Chen , Pin-Dai Sue
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater & Matsil, L.L.P.
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L21/768 ; H01L29/41
Abstract:
A circuit includes a semiconductor substrate; a bottom metal layer over the semiconductor substrate, wherein no additional metal layer is between the semiconductor substrate and the bottom metal layer; and a cell including a plug-level power rail under the bottom metal layer.
Public/Granted literature
- US20120280287A1 Integrated Circuit Layouts with Power Rails under Bottom Metal Layer Public/Granted day:2012-11-08
Information query
IPC分类:
