As provided herein, in some embodiments, power consumption and/or chip area is reduced by bias circuits configured to provide bias conditions for more than one active circuit, thereby reducing the number of bias circuits in a design. Shared bias circuits may reduce the aggregate amount of on-chip area utilized by bias circuitry and may also reduce the total power consumption of a chip. Additionally and/or alternatively, bias circuits disclosed herein are configured to provide outputs that are less susceptible to changes in the voltage supply level. In particular, in some embodiments, bias circuits are configured to provide relatively constant bias conditions despite changes in the voltage supply level. In some embodiments, bias circuits are configured to provide bias conditions that compensate for perturbations caused by changes other inputs, in order to stabilize a particular operating point.