Invention Grant
US08508969B2 Semiconductor device having hierarchically structured bit lines and system including the same
有权
具有分层结构的位线的半导体器件和包括该位线的系统
- Patent Title: Semiconductor device having hierarchically structured bit lines and system including the same
- Patent Title (中): 具有分层结构的位线的半导体器件和包括该位线的系统
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Application No.: US13533896Application Date: 2012-06-26
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Publication No.: US08508969B2Publication Date: 2013-08-13
- Inventor: Seiji Narui
- Applicant: Seiji Narui
- Applicant Address: JP Tokyo
- Assignee: Elpida Memory, Inc.
- Current Assignee: Elpida Memory, Inc.
- Current Assignee Address: JP Tokyo
- Agency: McGinn IP Law Group, PLLC
- Priority: JP2009-177404 20090730
- Main IPC: G11C5/06
- IPC: G11C5/06
Abstract:
A device includes a first sense amplifier array including a plurality of first sense amplifiers arranged in a first direction, each of the first sense amplifiers including first and second nodes, a plurality of first global bit lines extending in a second direction crossing the first direction, the first global bit lines being arranged in the first direction on a left side of the first sense amplifier array so that the first global bit lines being operatively connected to the first node of an associated one of the first sense amplifiers, and a plurality of second global bit lines extending in the second direction, the second global bit lines being arranged in the first direction on a right side of the first sense amplifier array so that the second global bit lines being operatively connected to the second node of the associated one of the first sense amplifiers.
Public/Granted literature
- US20120300529A1 SEMICONDUCTOR DEVICE HAVING HIERARCHICALLY STRUCTURED BIT LINES AND SYSTEM INCLUDING THE SAME Public/Granted day:2012-11-29
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