Invention Grant
- Patent Title: Low resistance high-TMR magnetic tunnel junction and process for fabrication thereof
- Patent Title (中): 低电阻高TMR磁隧道结及其制造方法
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Application No.: US12040801Application Date: 2008-02-29
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Publication No.: US08508984B2Publication Date: 2013-08-13
- Inventor: Rajiv Yadav Ranjan , Parviz Keshtbod , Roger Klas Malmhall
- Applicant: Rajiv Yadav Ranjan , Parviz Keshtbod , Roger Klas Malmhall
- Applicant Address: US CA Fremont
- Assignee: Avalanche Technology, Inc.
- Current Assignee: Avalanche Technology, Inc.
- Current Assignee Address: US CA Fremont
- Agency: IPxLAW Group LLP
- Agent Maryam Imam
- Main IPC: G11C11/00
- IPC: G11C11/00

Abstract:
A non-volatile magnetic memory element includes a fixed layer, a barrier layer formed on top of the fixed layer, and a free layer formed on top of the barrier layer, wherein the electrical resistivity of the barrier layer is reduced by placing said barrier layer under compressive stress. Compressive stress is induced by either using a compressive stress inducing layer, or by using inert gases at low pressure during the sputtering process as the barrier layer is deposited, or by introducing compressive stress inducing molecules into the molecular lattice of the barrier layer.
Public/Granted literature
- US20080164548A1 LOW RESISTANCE HIGH-TMR MAGNETIC TUNNEL JUNCTION AND PROCESS FOR FABRICATION THEREOF Public/Granted day:2008-07-10
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