Invention Grant
US08510493B2 Circuit to efficiently handle data movement within a cache controller or on-chip memory peripheral
有权
电路有效地处理高速缓存控制器或片上存储器外围设备内的数据移动
- Patent Title: Circuit to efficiently handle data movement within a cache controller or on-chip memory peripheral
- Patent Title (中): 电路有效地处理高速缓存控制器或片上存储器外围设备内的数据移动
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Application No.: US12978719Application Date: 2010-12-27
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Publication No.: US08510493B2Publication Date: 2013-08-13
- Inventor: Judy M Gehman , Jerome M Meyer
- Applicant: Judy M Gehman , Jerome M Meyer
- Applicant Address: US CA Milpitas
- Assignee: LSI Corporation
- Current Assignee: LSI Corporation
- Current Assignee Address: US CA Milpitas
- Agency: Suiter Swantz pc llo
- Main IPC: G06F13/14
- IPC: G06F13/14 ; G06F3/00
Abstract:
The present invention is directed to a circuit for managing data movement between an interface supporting the PLB6 bus protocol, an interface supporting the AMBA AXI bus protocol, and internal data arrays of a cache controller and/or on-chip memory peripheral. The circuit implements register file buffers for gathering data to bridge differences between the bus protocols and bus widths in a manner which addresses latency and performance concerns of the overall system.
Public/Granted literature
- US20120166730A1 CIRCUIT TO EFFICIENTLY HANDLE DATA MOVEMENT WITHIN A CACHE CONTROLLER OR ON-CHIP MEMORY PERIPHERAL Public/Granted day:2012-06-28
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