This disclosure concerns a memory system including: chips (MC00-MC37) laid out with erasure blocks, the erasure blocks respectively being formed by laying out with pages and being an erasure unit, the pages respectively being formed by laying out with cells; IO line groups connected to the chips, wherein the chips connected to the same IO line group form a memory group (MG0-MG3), and the memory group is divided into first to n-th sub-memory groups (BB-SGA to BB-SGD), and number of bad blocks of the chip having a smallest number of bad blocks in a k-th sub-memory group in the memory groups is larger than number of bad blocks of the chip having a largest number of the bad blocks in a (k+1)-th sub-memory group in the memory groups, the bad blocks are the erasure blocks in which erasing, writing or reading of data cannot be performed correctly.