Provided are a ring buffer circuit in which a data full state and a data empty state may be correctly detected without depending on whether read and write operations are synchronous or asynchronous with each other, and a control circuit for the ring buffer circuit. The ring buffer circuit includes: a read and write memory having addresses specified by N bits; a write address counter pointer and a read address counter pointer which are provided for the read and write memory to count (N+1)-bit gray codes; and write and read address converter circuits provided to convert the (N+1)-bit gray codes output from the write and read address counter pointers into N-bit addresses which may be directly designated as write and read addresses of the read and write memory.