Invention Grant
US08510641B2 Circuit and technique for reducing parity bit-widths for check bit and syndrome generation for data blocks through the use of additional check bits to increase the number of minimum weighted codes in the hamming code H-matrix
有权
通过使用附加校验位来增加汉明码H矩阵中的最小加权码的数量来减少用于数据块的校验位和校正子生成的校验位宽度的电路和技术
- Patent Title: Circuit and technique for reducing parity bit-widths for check bit and syndrome generation for data blocks through the use of additional check bits to increase the number of minimum weighted codes in the hamming code H-matrix
- Patent Title (中): 通过使用附加校验位来增加汉明码H矩阵中的最小加权码的数量来减少用于数据块的校验位和校正子生成的校验位宽度的电路和技术
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Application No.: US13564354Application Date: 2012-08-01
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Publication No.: US08510641B2Publication Date: 2013-08-13
- Inventor: Oscar Frederick Jones, Jr.
- Applicant: Oscar Frederick Jones, Jr.
- Applicant Address: US CA San Jose
- Assignee: Invensas Corporation
- Current Assignee: Invensas Corporation
- Current Assignee Address: US CA San Jose
- Agency: Lerner, David, Littenberg, Krumholz & Mentlik, LLP
- Main IPC: H03M13/00
- IPC: H03M13/00
Abstract:
A technique for reducing parity bit-widths for check bit and syndrome generation through the use of additional check bits to increase the number of minimum weighted codes in the Hamming Code H-Matrix. The technique of the present invention may be implemented while adding no additional correction/detection capability, in order to reduce the number of data bits that are used for each check bit/syndrome generation and to reduce the width of the parity generating circuitry.
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