Invention Grant
US08510691B2 Semiconductor verification apparatus, method and program 有权
半导体验证装置,方法和程序

  • Patent Title: Semiconductor verification apparatus, method and program
  • Patent Title (中): 半导体验证装置,方法和程序
  • Application No.: US13120622
    Application Date: 2009-10-08
  • Publication No.: US08510691B2
    Publication Date: 2013-08-13
  • Inventor: Kohei Hosokawa
  • Applicant: Kohei Hosokawa
  • Applicant Address: JP Tokyo
  • Assignee: NEC Corporation
  • Current Assignee: NEC Corporation
  • Current Assignee Address: JP Tokyo
  • Priority: JP2008-262299 20081008
  • International Application: PCT/JP2009/005241 WO 20091008
  • International Announcement: WO2010/041451 WO 20100415
  • Main IPC: G06F17/50
  • IPC: G06F17/50
Semiconductor verification apparatus, method and program
Abstract:
A semiconductor device which can only load a logical value of an arbitrary memory element is rendered possible to allow a logical value of an arbitrary signal to be loaded at a high speed. A circuit diagram of the semiconductor device is input and a memory element required for calculating a desired signal is detected. The logical value of the memory element is loaded from the semiconductor device, and the logical value of the desired signal is determined in accordance with the logical value of the memory element and the circuit configuration.
Public/Granted literature
Information query
Patent Agency Ranking
0/0