Some embodiments provide a system that analyzes the operation of a disassembler. The system starts by generating a set of processor instructions. Next, the system validates the disassembler using each processor instruction from the set of processor instructions by obtaining an assembly representation for the processor instruction using the disassembler. The system then monitors an execution of the processor instruction on a processor operating in single-step mode to produce an execution result for the processor instruction, and determines a correctness of the disassembler by comparing the assembly representation for the processor instruction with the execution result for the processor instruction.