A signal transfer circuit may include first to nth switches that are respectively connected to bits of an n-bit digital signal output from a digital signal generating circuit and controlled by a transfer control circuit, a first memory circuit including first to nth memories that respectively hold bits of the n-bit digital signal input through the first to nth switches and are serially connected to each other, a second memory circuit including (n+1)th to mth memories that hold a digital signal and are serially connected to each other, an output signal of the nth memory of the first memory circuit being input to the (n+1)th memory of a first stage, and (n+1)th to mth switches that are connected to output signals of the (n+1)th to mth memories of the second memory circuit and controlled by a read control circuit.