Invention Grant
US08524571B2 Vacuum wafer level packaging method for micro electro mechanical system device
有权
微电子机械系统装置的真空晶片级封装方法
- Patent Title: Vacuum wafer level packaging method for micro electro mechanical system device
- Patent Title (中): 微电子机械系统装置的真空晶片级封装方法
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Application No.: US13309582Application Date: 2011-12-02
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Publication No.: US08524571B2Publication Date: 2013-09-03
- Inventor: Jong Tae Moon , Yong Sung Eom , Hyun-Cheol Bae
- Applicant: Jong Tae Moon , Yong Sung Eom , Hyun-Cheol Bae
- Applicant Address: KR Daejeon
- Assignee: Electronics and Telecommunications Research Institute
- Current Assignee: Electronics and Telecommunications Research Institute
- Current Assignee Address: KR Daejeon
- Agency: Rabin & Berdo, P.C.
- Priority: KR10-2010-0133515 20101223
- Main IPC: H01L21/30
- IPC: H01L21/30 ; H01L21/46 ; H01L41/00

Abstract:
Disclosed is a vacuum wafer level packaging method for a micro electro mechanical system device, including: forming a plurality of via holes on an upper wafer for protecting a micro electro mechanical system (MEMS) wafer; forming at least one metal layer on inner walls of the plurality of via holes and regions extended from the plurality of via holes; arranging and bonding the upper wafer and the MEMS wafer at atmospheric pressure; applying solder paste to the regions extended from the plurality of via holes; filling a solder in the plurality of via holes by increasing the temperature of a high-vacuum chamber to melt the solder paste; and changing the solder in the plurality of via holes to a solid state by lowering the temperature of the high-vacuum chamber.
Public/Granted literature
- US20120164787A1 VACUUM WAFER LEVEL PACKAGING METHOD FOR MICRO ELECTRO MECHANICAL SYSTEM DEVICE Public/Granted day:2012-06-28
Information query
IPC分类: